1. Field of the Invention
This invention relates generally to a method of manufacturing high density, high performance semiconductor devices that have dual damascene interconnects. More specifically, this invention relates to a method of manufacturing high density, high performance semiconductor devices that have dual damascene interconnects using a phantom implant mask.
2. Discussion of the Related Art
The increased demand for higher performance semiconductor devices has required more complex process technologies and materials to be utilized in the manufacture of semiconductor integrated devices. One way to increase the performance of a semiconductor integrated device such as a microprocessor is to reduce the gate width of the field effect transistors in the device in order to achieve high internal clock speed for the microprocessor. The reduced gate widths have increased the performance significantly, however, the interconnect structure of the microprocessor has proved to be a roadblock to further increase in performance. This is because as increased performance is required, more transistors need to be manufactured in the semiconductor integrated device. These added transistors require more wiring in the interconnect structure. The increased density of the wiring can result in a decrease in performance relating to RC delays. To counteract the degradation in performance due to the RC delays, additional layers in which interconnects are formed are manufactured in order to separate the wiring in both the vertical and horizontal directions. These requirements have necessitated the development of novel approaches in the methods of forming interconnections that not only integrate fine geometry definition but also can be efficiently implemented into the manufacturing process.
One method if forming a trench is a method known as the damascene process, which comprises forming a trench by masking and etching techniques and subsequent filling of the trench with the desired conductive material. The damascene process is a useful method for attaining the fine geometry metallization required for advanced semiconductor devices. A dual damascene process is a two step sequential mask/etch process to form a two level structure such as a via connected to a metal line above the via.
Current dual damascene processing technology entails depositing a triple layer sandwich consisting of a thick layer of a dielectric material, an etch stop material having a high etch selectivity to the dielectric layer, and a second thick layer of a dielectric material. The two level structure is formed by masking and etching through the top layer of dielectric material stopping on the layer of etch stop material, etching the etch stop material only, then performing a second masking and etching process with the second masking being an oversize masking. The second etch process is to the dielectric material underlying the lower layer of dielectric material.
A problem with the current damascene process is the number of defects associated with the metal etch back process associated with damascene processing. The problem is the residual metal particles that may be left after the metal etch back that can short out the circuit. A single damascene process is used to etch trenches in an insulating dielectric material. A conductive material is deposited into these trenches and the excess polished using a chemical mechanical process. This method shows dramatic reduction of defects, however, this method is time consuming.
Therefore, what is needed is a method of forming the via structure and the trench structure together.